The use of parallel architecture in processors is a typical way to reduce power consumption without a performance penalty at the architectural level, see for example, “Low Power Digital CMOS Design, IEEE Journal of Solid State Circuits, pp. 473-484, April 1992. For a given performance level, the use of parallelism allows a task to be distributed and the frequency and voltage can typically be scaled down without performance losses.
There is a trend for multi-core architecture to be used even in small microcontrollers. The challenge is typically how to effectively and advantageously use the additional resources that are available in a multi-core architecture.
Many applications in the area of small microcontrollers are typically based on an interrupt that triggers the execution of multiple tasks. FIG. 1 shows system 100 that uses multiple peripherals connected to microcontroller (MCU) 110. In a given time interval, e.g. 1 ms, MCU 110 checks sensor 115, General Packet Radio Service (GPRS) modem 120 connectivity, Global Positioning System (GPS) 125 position, keyboard 140 for input, addresses actuator 130 and updates display 135 if needed. Typically, system 100 is implemented by setting up a timer (not shown) so that when the timer interrupt occurs, all tasks are executed. Explicit parallelism exists in system 100. For example, the tasks of checking sensor 115 and addressing actuator 130 are independent of checking GPRS modem 120 connectivity and GPS 125 position.
However, typical microcontrollers do not provide for the capability of distributing tasks to different cores for execution. The microcontroller code needs to be written to manage all the tasks at the same time while utilizing only one resource. If some tasks can be executed in a second core but still share common memory with the first core, the implementation is simplified while the power consumption may be reduced through voltage and frequency scaling without performance losses.
FIG. 2 shows typical multi-core architecture 200 where core 210, core 220 . . . and core 230 are connected and share common memory 240. Core 210 has peripherals 250, core 220 has peripherals 255 . . . and core 230 has peripherals 260 where each core 210, 220 . . . and 230 has its own memory 265, 270 . . . and 275, respectively.